Capability matrix
What each engine actually does, generated from the engines’ own registries. Verified means an automated test exercises the feature end to end (the evidence column names it). Experimental works in tests but the output isn’t validated beyond them, for example not yet tried on hardware or at a fabricator. Prototype means the code exists and is unit-tested, but the end-to-end path hasn’t run on the build host. Planned and unsupported mean exactly that.
| Status | Count |
|---|---|
| verified | 73 |
| experimental | 7 |
| prototype | 6 |
| planned | 24 |
| unsupported | 1 |
3D
| Capability | Status | Platforms | Requires | Evidence |
|---|---|---|---|---|
| 3D board model: substrate with cut-outs and drill holes, exact-width copper on every layer (tracks, pads, vias, zone fills), plated barrels, solder mask with openings, silkscreen, parametric package bodies and user model placements | verified | web, windows, macos, linux | — | test/mesh.test.ts |
| STEP (ISO 10303) board and component export | planned | — | — | — |
Collaboration
| Capability | Status | Platforms | Requires | Evidence |
|---|---|---|---|---|
| Validated, serialized collaborative transactions with entity-level conflict detection | verified | web, windows, macos, linux | — | test/collab.test.ts + test-vectors/collab (shared with falcad-cloud) |
Firmware
| Capability | Status | Platforms | Requires | Evidence |
|---|---|---|---|---|
| Built-in AVR assembler (core instruction subset, labels, .org/.equ/data directives) | verified | web, windows, macos, linux | — | test/assembler.test.ts |
| ATmega328P emulation: CPU, Timer0/1/2, GPIO ports B/C/D, USART0 and ADC, with pin-level events and simulated time | verified | web, windows, macos, linux | avr8js | test/avr-device.test.ts |
| Virtual serial monitor for the emulated USART0 (TX capture and RX injection) | verified | web, windows, macos, linux | avr8js | test/avr-device.test.ts |
| ARM Cortex-M emulation | planned | — | — | — |
| ESP32 emulation | planned | — | — | — |
| RP2040 emulation | planned | — | — | — |
| Compile Arduino sketches (arduino-cli compile, diagnostics, .hex location) | prototype | windows, macos, linux | arduino-cli, arduino:avr core | — |
| Compile C/C++ firmware with avr-gcc / arm-none-eabi-gcc directly | planned | — | avr-gcc, avr-objcopy | — |
| On-chip debugging via OpenOCD (ST-LINK) or pyOCD (CMSIS-DAP) | planned | — | openocd, pyocd | — |
| Flash/erase/verify real boards (avrdude) | prototype | — | avrdude | — |
| Intel HEX reader/writer (records 00-05, checksums, address gaps) | verified | web, windows, macos, linux | — | test/intel-hex.test.ts |
| Detect arduino-cli, avr-gcc, avr-objcopy, arm-none-eabi-gcc, avrdude, openocd and pyocd on PATH, with opt-in version probing | verified | windows, macos, linux | — | test/toolchain.test.ts |
HDL & FPGA
| Capability | Status | Platforms | Requires | Evidence |
|---|---|---|---|---|
| Formal verification (SymbiYosys) | planned | — | sby, SMT solver | — |
| Structural diagnostics | verified | web, windows, macos, linux | — | test/lang.test.ts |
| Verilog, SystemVerilog and VHDL lexers | verified | web, windows, macos, linux | — | test/lang.test.ts |
| Go to definition, find references, hierarchy and top-level detection | verified | web, windows, macos, linux | — | test/lang.test.ts |
| Outline indexer: units, ports, parameters/generics, instances, includes | verified | web, windows, macos, linux | — | test/lang.test.ts |
| Verilator lint | prototype | windows, macos, linux | verilator | — |
| ECP5 place and route | planned | — | @yowasp/nextpnr-ecp5 | — |
| iCE40 place and route + bitstream (nextpnr-ice40 + icepack, WebAssembly) | experimental | web, windows, macos, linux | @yowasp/nextpnr-ice40 | test/yosys.test.ts |
| Board programming with openFPGALoader | planned | — | openFPGALoader | — |
| Cycle-based simulation of synthesizable RTL (Yosys netlist + FalCAD gate simulator) | verified | web, windows, macos, linux | @yowasp/yosys | test/yosys.test.ts |
| VHDL simulation with GHDL | prototype | windows, macos, linux | ghdl | — |
| Event-driven Verilog simulation with Icarus Verilog | prototype | windows, macos, linux | iverilog, vvp | — |
| Event-driven Verilog simulation with Icarus Verilog (WebAssembly, optional package) | verified | web, windows, macos, linux | @veriflow/iverilog-wasm | test/iverilog-wasm.test.ts |
| SystemVerilog synthesis through the slang frontend | verified | web, windows, macos, linux | @yowasp/yosys | test/yosys.test.ts |
| VHDL synthesis | unsupported | — | ghdl, ghdl-yosys-plugin | — |
| Yosys synthesis for Lattice ECP5 | verified | web, windows, macos, linux | @yowasp/yosys | test/yosys.test.ts |
| Yosys synthesis (WebAssembly), generic gates | verified | web, windows, macos, linux | @yowasp/yosys | test/yosys.test.ts |
| Yosys synthesis for Lattice iCE40 | verified | web, windows, macos, linux | @yowasp/yosys | test/yosys.test.ts |
| Testbench skeleton generator (Verilog and VHDL) | verified | web, windows, macos, linux | — | test/testbench.test.ts |
| Safe native process runner and tool detection | verified | web, windows, macos, linux | — | test/process.test.ts, test/worker.test.ts |
| WebAssembly tool runs in Node worker threads with a deadline | verified | web, windows, macos, linux | @yowasp/yosys | test/process.test.ts, test/worker.test.ts |
| Streaming VCD parser, waveform model and VCD writer | verified | web, windows, macos, linux | — | test/vcd.test.ts |
Manufacturing
| Capability | Status | Platforms | Requires | Evidence |
|---|---|---|---|---|
| Bill of materials CSV grouped by value and footprint | verified | web, windows, macos, linux | — | test/assembly.test.ts |
| Excellon drill export: plated / non-plated / blind-buried spans, metric, tool table, X2-style attributes | verified | web, windows, macos, linux | — | test/gerber.test.ts |
| Gerber job file (.gbrjob) | planned | — | — | — |
| Gerber X2 export: copper, solder mask, paste, silkscreen (stroke-font references), board profile | verified | web, windows, macos, linux | — | test/gerber.test.ts |
| IPC-D-356 netlist for electrical test | planned | — | — | — |
| Fabrication job manifest with SHA-256 of every file (provenance) | verified | web, windows, macos, linux | — | test/fabrication.test.ts |
| ODB++ / IPC-2581 export | planned | — | — | — |
| Pick-and-place (centroid) CSV in the fabrication coordinate frame | verified | web, windows, macos, linux | — | test/assembly.test.ts |
| Panelization (step-and-repeat, rails, mouse bites, V-score) | planned | — | — | — |
Mechatronics
| Capability | Status | Platforms | Requires | Evidence |
|---|---|---|---|---|
| Parametric mechanical bodies (plate, box, cylinder, wheel, standoff, bracket, battery holder, gear motor) with built-in terminals | verified | web, windows, macos, linux | — | test/system.test.ts |
| System checks across boards: unconnected pins, joined supplies of different voltage or name, supplies shorted to ground, shorted outputs, wire ampacity, missing ground return, pins used twice, non-connector ends, parent loops, part interference (oriented boxes) | verified | web, windows, macos, linux | — | test/system.test.ts |
| System netlist of a 3D assembly: every board instance’s nets, qualified by instance, merged through external wires and mechanical terminals | verified | web, windows, macos, linux | — | test/system.test.ts |
| 3D wire paths through route points with bend radius, exact routed length, cut length with slack, cable BOM and cut list (CSV) | verified | web, windows, macos, linux | — | test/system.test.ts |
PCB
| Capability | Status | Platforms | Requires | Evidence |
|---|---|---|---|---|
| Create a board from a schematic: footprints linked by component, auto-placed on a non-overlapping grid | verified | web, windows, macos, linux | — | test/board.test.ts |
| Copper connectivity (pads, tracks, vias, zone fills), ratsnest as a per-net minimum spanning tree, unrouted count | verified | web, windows, macos, linux | — | test/connectivity.test.ts |
| Design rule check: clearance, track width, via drill/diameter/annular ring, hole-to-hole, board edge, outside board, unconnected, shorts, net mismatch, courtyards | verified | web, windows, macos, linux | — | test/drc.test.ts |
| Update an existing board from a changed schematic (add/remove/relink footprints) | planned | — | — | — |
| Controlled-impedance calculation from the stackup | planned | — | — | — |
| World-space pad geometry (footprint rotation, bottom-side mirroring, pad rotation) with nets from the schematic netlist | verified | web, windows, macos, linux | — | test/board.test.ts |
| Snap track ends to pads and place tracks with a DRC pre-check | prototype | web, windows, macos, linux | — | test/routing.test.ts |
| Length matching and differential pairs | planned | — | — | — |
| Grid A* router for a single two-point connection on one or two layers | experimental | web, windows, macos, linux | — | test/routing.test.ts |
| Interactive push-and-shove router | planned | — | — | — |
| Copper zone filling with clearance knock-outs, priorities and isolated-island removal | experimental | web, windows, macos, linux | — | test/zones.test.ts |
| Thermal relief spokes for zone connections | planned | — | — | — |
Schematic
| Capability | Status | Platforms | Requires | Evidence |
|---|---|---|---|---|
| Buses and bus entries | planned | — | — | — |
| Geometric connectivity and netlist extraction (wires, T-junctions, labels, power symbols, multi-sheet) | verified | web, windows, macos, linux | — | test/netlist.test.ts |
| Electrical rule check with configurable severities and suppressions that require a rationale | verified | web, windows, macos, linux | — | test/erc.test.ts |
| Hierarchical sheets with sheet pins | planned | — | — | — |
Simulation
| Capability | Status | Platforms | Requires | Evidence |
|---|---|---|---|---|
| AC small-signal analysis linearised at the operating point (log sweep, dB / phase) | verified | web, windows, macos, linux | — | test/analog.validation.test.ts |
| Convergence fallbacks: gmin stepping and source stepping, with a convergence report | verified | web, windows, macos, linux | — | test/analog.robustness.test.ts |
| DC sweep of an independent source | verified | web, windows, macos, linux | — | test/analog.validation.test.ts |
| Singular-circuit diagnostics naming nets: floating node, voltage-source loop, current-source cut-set | verified | web, windows, macos, linux | — | test/analog.robustness.test.ts |
| Fourier / THD of transient probes (SPICE .four-style, last N periods) | verified | web, windows, macos, linux | — | test/analyses.validation.test.ts |
| User initial conditions per node (.ic) | planned | — | — | — |
| Monte Carlo (uniform / gaussian tolerances, seeded xoshiro128**, OS-CSPRNG seed recorded in provenance, statistics, yield) | verified | web, windows, macos, linux | — | test/analyses.validation.test.ts |
| Noise analysis: output and input-referred noise density by the adjoint method; resistor thermal and diode shot noise | verified | web, windows, macos, linux | — | test/analyses.validation.test.ts |
| Noise sources of BJTs (shot noise of Ic and Ib, thermal noise of RB / RC / RE) and FETs (channel 8kT·gm/3) | experimental | web, windows, macos, linux | — | test/analyses.validation.test.ts |
| DC operating point (Newton–Raphson with damping and junction limiting) | verified | web, windows, macos, linux | — | test/analog.validation.test.ts |
| Pole-zero and sensitivity analysis | planned | — | — | — |
| Sparse LU with minimum-degree ordering (thousands of nodes) | verified | web, windows, macos, linux | — | test/sparse.test.ts |
| Parameter and temperature stepping of any analysis (analysis sweep), with per-step assertions | verified | web, windows, macos, linux | — | test/analyses.validation.test.ts |
| Circuit temperature: IS(T) of diodes and BJTs, thermal voltage, BF / BR (XTB) | verified | web, windows, macos, linux | — | test/semiconductor.validation.test.ts |
| Transient analysis: trapezoidal and backward Euler, LTE step control, waveform breakpoints, event location, zero-state start | verified | web, windows, macos, linux | — | test/analog.validation.test.ts |
| Arbitrary behavioural (expression) sources | planned | — | — | — |
| Bipolar transistors NPN / PNP: Gummel–Poon subset (IS, BF, BR, NF, NR, VAF, VAR, IKF, IKR, ISE, NE, ISC, NC, RB, RC, RE, CJE, CJC, TF, TR, EG, XTI, XTB) | verified | web, windows, macos, linux | — | test/semiconductor.validation.test.ts |
| Comparator: push-pull or open-collector output, optional hysteresis (located thresholds) | verified | web, windows, macos, linux | — | test/active.validation.test.ts |
| VCCS, CCCS and CCVS (current-controlled sources with a zero-volt sense port) | verified | web, windows, macos, linux | — | test/passive.validation.test.ts |
| Shockley diode with series resistance, emission coefficient, gmin, pnjlim | verified | web, windows, macos, linux | — | test/analog.validation.test.ts |
| Diode junction capacitance (CJO, VJ, M, FC), transit time (TT), reverse breakdown (BV, IBV, NBV), zener, temperature (EG, XTI) | verified | web, windows, macos, linux | — | test/semiconductor.validation.test.ts |
| JFETs N / P: Shichman–Hodges with gate junctions and capacitances | verified | web, windows, macos, linux | — | test/semiconductor.validation.test.ts |
| MOSFETs N / P: level 1 (Shichman–Hodges) with body effect, channel-length modulation, body diodes, constant gate capacitances | verified | web, windows, macos, linux | — | test/semiconductor.validation.test.ts |
| Op-amps: ideal (high-gain VCVS) and macromodel (gain, GBW single pole, slew rate, rail swing, input offset, output resistance, supply currents) | verified | web, windows, macos, linux | — | test/active.validation.test.ts |
| Resistor, capacitor, inductor, static switch (ron / roff) | verified | web, windows, macos, linux | — | test/analog.validation.test.ts |
| Potentiometer (lin / log taper), coupled inductors, ideal and coupled transformer, lamp, fuse (non-destructive rating warning), crystal (BVD), SPDT switch, relay (pull-in / drop-out hysteresis), battery, ammeter, voltmeter | verified | web, windows, macos, linux | — | test/passive.validation.test.ts |
| Linear regulators (7805 fixed, LM317 adjustable): dropout, ground / ADJ current, load regulation, current limit | verified | web, windows, macos, linux | — | test/active.validation.test.ts |
| Independent V / I sources: DC, PULSE, SIN, PWL, EXP, SFFM | verified | web, windows, macos, linux | — | test/waveform.test.ts |
| 555 timer (behavioural): divider, comparators, latch, discharge, output stage | verified | web, windows, macos, linux | — | test/active.validation.test.ts |
| Voltage-controlled voltage source | verified | web, windows, macos, linux | — | test/analog.robustness.test.ts |
| Live interactive session: frame-paced advance, live inputs (switches, buttons, potentiometers, sources, logic inputs), readouts, scope ring buffer, warm restart on rebuilds | verified | web, windows, macos, linux | — | test/live.test.ts |
| Event-driven 4-state logic simulation (gates, DFF, clock, inputs, probes, wired nets) | verified | web, windows, macos, linux | — | test/digital.test.ts |
| Logic IC behaviours: 74HC74 / 161 / 163 / 138 / 151 / 157 / 164 / 595, CD4017, buffer | verified | web, windows, macos, linux | — | test/ics.test.ts |
| Combinational-loop / ring-oscillator detection and zero-delay oscillation guard | verified | web, windows, macos, linux | — | test/digital.test.ts |
| VCD waveform export | verified | web, windows, macos, linux | — | test/digital.test.ts |
| ATmega328P / Arduino Uno co-simulation (AvrDevice from @falcad/mcu): GPIO drivers and thresholds, pull-ups, ADC, PWM / timers, serial, brown-out | verified | web, windows, macos, linux | — | test/mixed.test.ts |
| Mixed-signal co-simulation: logic parts on analog nets through push-pull drivers (supply-referenced or ideal) and Schmitt thresholds, lock-step at logic events | verified | web, windows, macos, linux | — | test/mixed.test.ts |
| Run decks with a locally installed ngspice (batch mode, sandboxed spawn) | experimental | windows, macos, linux | ngspice (native executable on PATH) | test/ngspice.test.ts |
| Min/max decimation of long series for plotting | verified | web, windows, macos, linux | — | test/render.test.ts |
| SimulationDocument runner: analyses, probes, assertions, provenance, JSON results | verified | web, windows, macos, linux | — | test/run.test.ts |
| Schematic → circuit mapping with exclusion diagnostics and net / component cross-probing map | verified | web, windows, macos, linux | — | test/schematic.test.ts |
| Export to an ngspice-compatible SPICE deck | experimental | web, windows, macos, linux | — | test/spice.test.ts |
| SPICE netlist / .model / .subckt import | planned | — | — | — |
| ASCII rawfile parser (real and complex plots) | experimental | web, windows, macos, linux | — | test/spice.test.ts |
| Multi-part ICs from library data (sim.parts): 74HC logic, LM358, LM393, PC817 | verified | web, windows, macos, linux | — | test/library-parts.test.ts |